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PRELIMINARY TECHNICAL DATA
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Preliminary Technical Data
FEATURES High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036 Less than 0.1% Error Over a Dynamic Range of 500 to 1 Compatible with 3-phase/3-wire and 3-phase/4-wire configurations The ADE7752 Supplies Average Real Power on the Frequency Outputs F1 and F2 The High Frequency Output CF Is Intended for Calibration and Supplies Instantaneous Real Power The Logic Output REVP indicates a Potential Miswiring or Negative Power for each phase Direct Drive for Electromechanical Counters and Two Phase Stepper Motors (F1 and F2) Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time On-Chip Power Supply Monitoring On-Chip Creep Protection (No Load Threshold) On-Chip Reference 2.5 V 8% (30 ppm/8C Typical) with External Overdrive Capability Single 5 V Supply, Low Power (15 mW Typical) Low Cost CMOS Process
ThreePhaseEnergyMeteringIC withPulseOutput ADE7752*
GENERAL DESCRIPTION
The ADE7752 is a high accuracy three phase electrical energy measurement IC. The part specifications surpass the accuracy requirements as quoted in the IEC1036 standard. The only analog circuitry used in the ADE7752 is in the ADCs and reference circuit. All other signal processing (e.g., multiplication, filtering and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752 supplies average real power information on the low frequency outputs F1 and F2. These logic outputs may be used to directly drive an electromechanical counter or interface with an MCU. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes, or as interface with an MCU. The ADE7752 includes a power supply monitoring circuit on the AVDD supply pin. The ADE7752 will remain inactive until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the ADE7752 will also be reset and no pulses will be issued on F1, F2 and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no-load threshold ensures that the ADE7752 does not exhibit any creep when there is no load. The ADE7752 is available in 24-lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAM
RESET
17
VDD
3
IAP 5 IAN 6 VAP 16
ADC ADC
HPF
LPF
PHASE CORRECTION
Power Supply Monitor
ADE7752
LPF
IBP 7 IBN 8 VBP 15
ADC ADC
HPF
2 19 20
PHASE CORRECTION
DGND CLKIN CLKOUT
ICP ICN 10 VCP 14 VN 13 2.5V REF
11
ADC ADC
HPF
LPF
PHASE CORRECTION
4k
12
DIGITAL-TO-FREQUENCY CONVERTER
4
18
21
22
23
24
1
*Patents pending
AGND
REF IN/OUT
REVP SCF S0
S1
F2 F1
CF
REV. PrB 08/01
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
PRELIMINARY TECHNICAL DATA
ADE7752-SPECIFICATIONS
Parameter ACCURACY Measurement Error1 on Current Channel 0.1 Phase Error1 Between Channels (PF = 0.8 Capacitive) (PF = 0.5 Inductive) AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error1 Gain Error Match1 REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS3 SCF, S0, S1, and 4-5-6 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH 4.5 Output Low Voltage, VOL 0.5 CF and REVP Output High Voltage, VOH Output Low Voltage, VOL 4 0.5 0.1 0.1 0.01
1, 2
(VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, TMIN to TMAX = -40 C to +85 C)
Test Conditions/Comments Voltage Channel with Full-Scale Signal (500 mV), +25C Over a Dynamic Range 500 to 1 Line Frequency = 45 Hz to 65 Hz
Units
% Reading typ Degrees() max Degrees() max % Reading typ
0.01
% Reading typ
S0 = S1 = 1 V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz Ripple on VDD of 200 mV rms @ 100 Hz S0 = S1 = 1 V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V 250 mV See Analog Inputs Section VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP and ICN to AGND CLKIN = 10 MHz CLKIN/256, CLKIN = 10 MHz See Terminology and External 2.5 V Reference, V1 = 125 mV dc, V2 = 125 mV dc External 2.5 V Reference 2.5 V + 8% 2.5 V - 8%
0.125 400 TBD 15 4 0.2 2.7 2.3 3.7 10 200 30 15 5
V max k min kHz typ mV max % Ideal typ % Ideal typ V max V min k min pF max mV max ppm/C typ
Nominal 2.5 V
Note All Specifications for CLKIN of 10 MHz MHz max MHz min
2.4 0.8 3 10
V min V max A max pF max
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
V min V max V min V max
ISOURCE = 10 mA VDD = 5 V ISINK = 10 mA VDD = 5 V VDD = 5 V, ISOURCE = 5 mA VDD = 5 V, ISINK = 5 mA
POWER SUPPLY VDD IDD
4.75 5.25 4
V min V max mA typ
For Specified Performance 5 V - 5% 5 V + 5%
NOTES 1 See Terminology Section for explanation of specifications. 2 See Plots in Typical Performance Graphs. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
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REV. PrB 08/01
PRELIMINARY TECHNICAL DATA ADE7752 TIMING CHARACTERISTICS1, 2 (V T
Parameter t13 t2 t3 t43, 4 t5 t6 275 See Table III 1/2 t2 90 See Table IV CLKIN/4 Units ms sec sec ms sec sec
DD MIN
= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, to TMAX = -40 C to +85 C)
Test Conditions/Comments F1 and F2 Pulsewidth (Logic High) Output Pulse Period. See Transfer Function Section Time Between F1 Falling Edge and F2 Falling Edge CF Pulsewidth (Logic High) CF Pulse Period. See Transfer Function Section Minimum Time Between F1 and F2 Pulse
NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 2 See Figure 1. 3 The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section. 4 The CF pulse is always 1 s in the high frequency mode. See Frequency Outputs section and Table IV. Specifications subject to change without notice.
t1
ORDERING GUIDE
F1 t6 t2
Model
Package Description
Package Option R-24
F2 t4 CF
t3 t5
ADE7752AR SOIC Package EVAL-ADE7752EB ADE7752 Evaluation Board
Figure 1. Timing Diagram for Frequency Outputs
REV. PrB 08/01
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PRELIMINARY TECHNICAL DATA ADE7752
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, . . . . . . . . . . . . . . . . . . IBP, IBN, ICP and ICN . . . . . . . . . . . . . -6 V to +6 V Reference Input Voltage to AGND -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C
24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . 250 C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7752 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
MEASUREMENT ERROR
ADC OFFSET ERROR
The error associated with the energy measurement made by the ADE7752 is defined by the following formula:
Percentage Error =
Energy Registered by the ADE7752 - True Energy x 100 % True Energy
PHASE ERROR BETWEEN CHANNELS
This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see an analog input signal of 1 mV to 10 mV, depending on gain setting. However, as the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset.
GAIN ERROR
The HPF (High Pass Filter) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels a phase correction network is also placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45Hz to 65Hz and 0.2 over a range 40Hz to 1kHz. This phase mismatch between the voltage and the current channels can be further reduced with the phase calibration register in each phase. See Figures 18 and 19.
POWER SUPPLY REJECTION
The gain error of the ADE7752 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752 transfer function--see Transfer Function section.
This quantifies the ADE7752 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement a reading at nominal supplies (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supplies and a second reading obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading--see Measurement Error definition. For the dc PSR measurement a reading at nominal supplies (5 V) is taken. The supply is then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
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REV. PrB 08/01
PRELIMINARY TECHNICAL DATA ADE7752
PIN FUNCTION DESCRIPTION
Pin No. 1
MNEMONIC CF
DESCRIPTION Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. Also see SCF pin description. This provides the ground reference for the digital circuitry in the ADE7752, i.e. multiplier, filters and digital-to-frequency converter. Because the digital return currents in the ADE7752 are small, it is acceptable to connect this pin to the analog ground plane of the whole system - see Applications Information. However high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance. Power supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply voltage should be maintained at 5V 5% for specified operation. This pin should be decoupled to DGND with a 10F capacitor in parallel with a ceramic 100nF capacitor. This logic output will go logic high when negative power is detected on any of the three phase inputs, i.e., when the phase angle between the voltage and the current signals is greater that 90. This output is not latched and will be reset when positive power is once again detected. The output will go high or low at the same time as a pulse is issued on CF. Analog inputs for current channel. This channel is intended for use with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.125V -See Analog Inputs. Both inputs have internal ESD protection circuitry, and in addition an overvoltage of 6V can be sustained on these inputs without risk of perma nent damage. This pin provides the ground reference for the analog circuitry in the ADE7754, i.e. ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage transducers etc. In order to keep ground noise around the ADE7754 to a minimum, the quiet ground plane should only connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane - see Applications Information. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5V 8% and a typical temperature coefficient of 30ppm/C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1F ceramic capacitor. Analog inputs for the voltage channel. This channel is intended for use with the voltage transducer and is referenced as the voltage channel in this document. These inputs are single-ended voltage inputs with maximum signal level of 0.125V with respect to VN for specified operation. All inputs have internal ESD protection circuitry, and in addi tion an over voltage of 6V can be sustained on these inputs without risk of permanent damage. Reset pin for the ADE7752. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface) in a reset condition. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table IV shows how the calibration frequencies are selected.
2
DGND
3
VDD
4
REVP
5,6; 7,8; 9,10
IAP, IAN; IBP, IBN; ICP, ICN
11
AGND
12
REFIN/OUT
13-16
VN,VCP, VBP, VAP
17 18
RESET SCF
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PRELIMINARY TECHNICAL DATA ADE7752
Pin No. 19 MNEMONIC CLKIN DESCRIPTION Master clock for ADCs and digital signal processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752. The clock frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers data sheet for load capacitance requirements A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7752. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. These logic inputs are used to select one of four possible frequencies for the digital-tofrequency conversion. This offers the designer greater flexibility when designing the energy meter. See Selecting a Frequency for an Energy Meter Application section. Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and two phase stepper motors. See Transfer Function section.
20
CLKOUT
21, 22
S0, S1
23, 24
F2, F1
PIN CONFIGURATION
SOIC Package
CF 1 DGND 2 VDD
3
24 F1 23 F2 22 S1 21 S0
REVP 4 IAP
5
ADE7752
20 CLKOUT
IAN 6
19 CLKIN TOP VIEW IBP 7 (Not to Scale) 18 SCF 17 RESET 16 VAP 15 VBP 14 VCP 13 VN
IBN 8 ICP 9 ICN 10 AGND 11 REFIn/Out 12
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REV. PrB 08/01
PRELIMINARY TECHNICAL DATA ADE7752
Meter connections
Ra* Rb* VAP VR* IAP Cf
In three phase service, two main power distribution services exist: 3-phase 4-wire or 3-phase 3-wire. The additional wire in the 3-phase 4-wire arrangement is the Neutral wire. The voltage lines have a phase difference of 120 ( 2/3 radians) between each other - See Equation 5.
Phase A
Anti-aliasing Filters
Rb CT
IAN
VA (t ) = 2 VA cos( l t )
;
VB (t ) = 2 VB cos( l t +
2 ) 3 (5)
Phase C
4 ) VC (t ) = 2 VC cos( l t + 3
Source
Phase B
CT
Rf Cf
VN
Load
Where: VA, VB and VC represent the voltage RMS value of the different phases The current inputs are represented by Equations 6,
I A (t ) = 2 I A cos( l t + A ) IC (t ) = 2 IC cos( l t +
4 + C ) 3 ;
Ra* Rb* Cf
Rb
IBP
Anti-aliasing Filters
IBN
IB (t ) = 2 IB cos( l t +
2 + B ) 3
VBP VR*
(6) Figure 14 - 3-phase 3-wire meter connection with ADE7752
Where: IA, IB and IC represent the RMS value of the current of each phase and A, B and C the phase difference of the current and voltage channel of each phase. The instantaneous powers can then be calculated as follows:
Note: Only 2 current inputs and 2 voltage inputs of the ADE7752 are used in this case. The Real power calculated by the ADE7752 does not depend on the selected channel. Figure 15 demonstrates the connections of the analog inputs of the ADE7752 with the power lines in a 3-phase 4-wire Wye service.
Ra* Rb* Cf
PA (t ) = VA (t ) I A (t ) PB (t ) = VB (t ) IB (t ) PC (t ) = VC (t ) IC (t )
Then,
PA (t ) = VA I A cos( A ) - VA I A cos( 2 l t + A ) 4 + B ) (7) PB (t ) = VB IB cos(B ) - VB IB cos( 2 l t + 3 8 + C ) PC (t ) = VC IC cos(C ) - VC IC cos(2 l t + 3
VAP VR* IAP
Anti-aliasing Filters
Rb CT
IAN
CT
Phase A
As can be seen from Equation 7, in the ADE7752 the real power calculation per phase is made when current and voltage inputs of the one phase are connected to the same channel (A, B or C). Then, the summation of each individual real power calculation gives the total Real Power information. P(t) = PA(t) + PB(t) + PC(t) Figure 14 demonstrates the connections of the analog inputs of the ADE7752 with the power lines in a 3-phase 3-wire Delta service.
Source
Phase B
Ra* Rb*
Cf
Rb
IBP
Anti-aliasing Filters
IBN VBP
Phase C
CT
VR*
Ra* Rb* VR*
Cf
Rb
ICP
Anti-aliasing Filters
ICN VCP
Load
Rf Cf
VN
Figure 15 - 3-phase 4-wire meter connection with ADE7752
REV. PrB 08/01
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PRELIMINARY TECHNICAL DATA ADE7752
TRANSFER FUNCTION Frequency Outputs F1 and F2 Example 1
The ADE7752 calculates the product of six voltage signals (on Current channel and Voltage channel) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active high pulses. The pulse rate at these outputs is relatively low, e.g., 0.08 Hz maximum for AC signals with SCF = S0 = S1 = 1--see Table III. This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation.
Freq =
109.2 x ( AN x I A + VBN x I B + VCN x IC ) x F 1 - 5 V
Thus if full-scale differential DC voltages of +125 mV and - 125 mV are applied to VA, VB, VC, IA, IB and IC respectively (125 mV is the maximum differential voltage that can be connected to Current and Voltage channels), the expected output frequency is calculated as follows: F1-5 = 0.596 Hz, SCF = S0 = S1 = 1 = +125 mV dc = 0.125 V (rms of dc = dc) VREF = 2.5 V (nominal reference value). NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%.
VAN = VBN = VCN = IA = IB = IC
Freq = 3 x
Example 2
109.2 x 0.125 x 0.125 x 0.596 = 0.488 Hz 2.5 2
VREF 2
where: Freq = Output frequency on F1 and F2 (Hz) VAN, VBN and VCN = Differential rms voltage signal on Voltage channels (volts) IA, IB and IC VREF F1-5 = = = Differential rms voltage signal on Current channels (volts) The reference voltage (2.5 V 8%) (volts) One of five possible frequencies selected by using the logic inputs SCF, S0 and S1--see Table II.
Table II. F1-5 Frequency Selection
In this example, with AC voltages of 500 mV peak applied to the Voltage channels and Current channels, the expected output frequency is calculated as follows: F1-5 = 0.596 Hz, SCF = S0 = S1 = 1 = 125 mV peak AC = 0.125/ 2 volts rms VREF = 2.5 V (nominal reference value). NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. VAN = VBN = VCN = IA = IB = IC
Freq = 3 x
109 .2 x 0.125 x 0.125 x 0.596 2 x 2 x 2.5 2
= 0.24 Hz
SCF 1 0 -
S1 1 1 1 0 0
S0 1 1 0 1 0
F1-5 (Hz) 0.596 76.3 19.07 4.77 1.19
XTAL/CLKIN* 10 10 10 10 10 MHz/224 MHz/217 MHz/219 MHz/221 MHz/223 As can be seen from these two example calculations, the maximum output frequency for AC inputs is always half of that for DC input signals. The maximum frequency depends also on the number of phases connected to the ADE7752. In a 3-phase 3-wire delta service the maximum output frequency is different from the maximum output frequency in a 3-phase 4-wire Wye service. The reason is that there are only 2 phases connected to the analog inputs but also that in a delta service, the Current channel input and Voltage channel input of the same phase are not in phase in normal operation.
Example 3
NOTE *F1-5 is a binary fraction of the master clock and therefore will vary if the specified CLKIN frequency is altered.
In this example, the ADE7752 is connected to a 3-phase 3wire delta service as shown in Figure 14. The total real energy calculation processed in the ADE7752 can be expressed as:
Total Re al Energy = (VA - VC ) x I A + (VB - VC ) x IB
Where VA, VB and VC represent respectively the voltage on phase A, B and C. IA and IB represent respectively the current on phase A and B. As the voltage and current inputs respect Equations 5 and 6, the Total Real Energy (P) is:
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REV. PrB 08/01
PRELIMINARY TECHNICAL DATA ADE7752
P = (VA - VC ) x (IAP - IAN ) + (VB - VC ) x (IBP - IBN ) P=
4 2 VA cos( l t ) - 2 VC cos l t + 2 I A cos( l t ) 3 2 4 2 + 2 VB cos l t + - 2 VC cos l t + 2 IB cos l t + 3 3 3
Table III. Maximum Output Frequency on F1 and F2
SCF 1 0 -
S1 1 1 1 0 0
S0 1 1 0 1 0
Max Frequency for DC Inputs (Hz) 0.48 62.52 15.6 3.9 0.96
Max Frequency for AC Inputs (Hz) 0.24 31.26 7.8 1.95 0.48
For simplification, we assume that A = B = C = 0 and VA = VB =VC = V. The equation above becomes:
P
2 2 = 2 V I A sin sin l t + cos ( l t ) 3 3 2 + 2 V IB sin sin ( l t + ) cos l t + 3 3
(9)
Frequency Output CF
P then becomes:
P
2 2 = VAN I A sin + sin 2 l t + 3 3 + VBN IB sin + sin 2 l t + 3 3
(10)
Where: VAN = V . sin(2/3) represents the RMS voltage between VAP and VN pins of the ADE7752 VBN = V . sin (/3) represents the RMS voltage between VBP and VN pins of the ADE7752. As the LPF on each channel eliminates the 2l component of the equation, the Real power measured by the ADE7752 is:
The pulse output CF (Calibration Frequency) is intended for use during calibration. The output pulse rate on CF can be up to 160 times the pulse rate on F1 and F2. The lower the F1-5 frequency selected, the higher the CF scaling. Table IV shows how the two frequencies are related, depending on the states of the logic inputs S0, S1 and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous real power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Hence less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations--see Signal Processing Block in Figure 8.
Table IV. Maximum Output Frequency on CF
SCF
P = VAN
3 3 IA + VBN IB 2 2
S1 0 0 0 0 1 1 1 1
S0 F1-5 (Hz) 0 0 1 1 0 0 1 1 1.19 1.19 4.77 4.77 19.07 19.07 76.29 0.596
CF Max for AC Signals (Hz) 160 x F1, F2 = 78.12 8 x F1, F2 = 3.90 160 x F1, F2 = 312.51 16 x F1, F2 = 31.26 16 x F1, F2 = 130.56 8 x F1, F2 = 62.49 8 x F1, F2 = 250 16 x F1, F2 = 3.90 Hz
Where: VAN and VBN are the voltage RMS at the voltage inputs of the ADE7752 after voltage sensing IA and IB are the voltage RMS at the current input of the ADE7752 after current sensing If full scale AC voltage of 125 mV peak are applied to the Voltage channels and Current channels, the expected output frequency is calculated as follows: F1-5 = 0.596 Hz, SCF = S0 = S1 = 1 = 125 mV peak AC = 0.125/ 2 volts rms VCN = IC = 0 VREF = 2.5 V (nominal reference value). NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%.
Freq = 2 x
109.2 x 0.125 x 0.125 x 0.596 3 x = 0.14 2 2 x 2 x 2.5 2
0 1 0 1 0 1 0 1
Frequency Outputs
VAN = VBN = IA = IB
Figure 1 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating high going pulses. The pulsewidth (t1) is set at 275 ms and the time between the rising edges of F1 and F2 (t3) is approximately half the period of F1 (t2). If however the period of F1 and F2 falls below 550 ms (1.81 Hz) the pulsewidth of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table III. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 90 ms-wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table IV. As in the case of F1 and F2, if the period of CF (t5) falls below 180 ms, the CF pulsewidth is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulsewidth is 25 ms.
Table III shows a complete listing of all maximum output frequencies when using all three channels inputs.
REV. PrB 08/01
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PRELIMINARY TECHNICAL DATA ADE7752
NO LOAD THRESHOLD NOTE
The ADE7752 also includes a "no load threshold" and "start-up current" feature that will eliminate any creep effects in the meter. The ADE7752 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2 or CF. The minimum output frequency is given as 0.0007% of the full-scale output frequency for each of the F 1-5 frequency selections--see Table II. For example, an energy meter with a meter constant of 100 imp/ kWhr on F1, F2 using F2 (4.77 Hz), the minimum output frequency at F1 or F2 would be 0.0007% of 4.77 Hz or 33.3 x 10-6 Hz. This would be 533 x 10-6 Hz at CF (16 x F1 Hz). In this example the no load threshold would be equivalent to 1.2 W of load or a start-up current of 5.5 mA at 220 V.
REVERSE POWER INFORMATION
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The ADE7752 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90 i.e. A or B or C > 90. This mechanism can detect wrong connection of the meter or generation of Active Energy. The REVP pin output will go active high when negative power is detected on any of the three phase inputs. If positive Active Energy is detected on all the three phases, REVP pin output is Low. The REVP pin output changes state at the same time as a pulse is issued on CF. If several phases measure negative power, the REVP pin output will stay low until all the phases measure positive power.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-SOIC Outline Package (AR-24)
0.6141 (15.60) 0.5985 (15.20)
24
13
0.2992 (7.60) 0.2914 (7.40)
1 12
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-10-
REV. PrB 08/01

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